1. Field of the Invention
The present invention relates to a method for fabricating a flash memory device, and more particularly, to a method for fabricating a memory transistor having floating gates disposed on vertical sidewalls of a control gate thereof.
2. Description of the Prior Art
Flash memory is known in the art. Flash memory is non-volatile, which means that it does not need power to maintain the information stored in the chip. In addition, flash memory offers fast read access times and better kinetic shock resistance than hard disks. Those characteristics explain the popularity of flash memory for applications of memory storage including digital audio players, digital camera, mobile cell phone, and USB flash drivers, etc.
FIGS. 1-4. illustrate a conventional method for fabricating floating gates on sidewalls of a control gate of a flash memory device. As shown in FIG. 1, a plurality of gate structures 12 are formed on a substrate 10. The substrate 10 may be a bulk semiconductor such as silicon substrate, but not limited thereto. Each gate structure 12 comprises a gate conductive layer 122, a gate dielectric layer 124 between the gate conductive layer 122 and the substrate 10, a dielectric layer 126, a polysilicon cap layer 128 on the dielectric layer 126, and an insulator layer 125 on the vertical sidewalls of the gate conductive layer 122.
The gate conductive layer 122 may comprise doped polysilicon. The gate dielectric layer 124 may comprise silicon oxide layer. The insulator layer 125 may comprise combinations of nitride silicon and silicon oxide layer, for example, oxide-nitride-oxide (ONO) dielectric layer. The dielectric layer 126 on the gate conductive layer 122 may be a silicon oxide layer.
The aforesaid gate structures 12 comprise adjacent gate 12a, gate 12b and gate 12c. The gate 12b is between the gate 12a and gate 12c, and the gate 12b is closer to the gate 12a than to the gate 12c. A liner 14 is then formed on the surface of the substrate 10 and the gate structures 12.
As shown in FIG. 2, a polysilicon layer 16 is blanket deposited on the surface of the substrate 10. The polysilicon layer 16 covers the gate structures 12 and fills the spacing between the gate structures 12. Thereafter, the polysilicon layer 16 is etched until the top surface of the polysilicon layer 16 is lower than the top of the gate conductive layer 122. At this point, as indicated in FIG. 2, the gate structures 12 protrude from the top surface of the polysilicon layer 16 by a predetermined height.
Subsequently, a chemical vapor deposition (CVD) process is carried out to blanket deposit a silicon nitride layer 18 on the substrate 10 to cover the top surface of the polysilicon layer 16 and the protruding top portions of the gate structures 12.
As shown in FIG. 3, an anisotropic etching process is carried out to etch the silicon nitride layer 18 until the polysilicon layer 16 and the liner 14 are exposed, thereby forming silicon nitride spacers 19 on sidewalls of the protruding top portions of the gate structures 12.
As shown in FIG. 4, using the silicon nitride spacer 19 as an etch mask, a dry etching process is performed to etch polysilicon layer 16 and the liner 14 so as to form self-aligned floating gates 20 on sidewalls of the gate structures 12, meanwhile the polysilicon cap layer 128 and part of the dielectric layer 126 above the gate structures 12 are etched away, resulting in a recessed top profile of the gate structures 12.
One drawback of the above-described conventional process for fabricating the sidewall floating gate by using the silicon nitride spacer 19 as mask to etch the polysilicon layer 16 is that the resultant floating gates may have so-called tailing defects, as specifically indicated by circles 30 in FIG. 4. The gate structures 12 are normally not evenly distributed on a wafer which leads to different etching environments across the wafer and thus different etching profiles of the floating gates. For example, the distance between the gate 12b and the gate 12c is larger than between the gate 12b and the gate 12a. This causes the difficulty of the etching recipe control and a vertical sidewall profile (especially at the bottom) of the floating gate 20 becomes a real challenge.
Furthermore, when etching the floating gates, a thickness of the silicon nitride spacer 19 is concurrently etched away. Thus, it is difficult to precisely control the thickness and the profile of the floating gate 20, leading to undesired thickness variation of the floating gates. It would thus be highly desirable to provide an improved method for fabricating floating gates on sidewalls of a control gate of a memory transistor in order to avoid these drawbacks.